1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an ESD (Electrostatic Discharge) protection region on a semiconductor device.
2. Description of the Related Art
A semiconductor device, such as a memory circuit, commonly includes an ESD protection circuit. A semiconductor device could be damaged by momentarily high voltage applied through a pad layer. A momentary high voltage that is made by a human body or a machine is called as ESD (ElectroStatic discharge). An ESD protection circuit is provided for preventing a memory device from being damaged by the ESD. An ESD protection circuit is usually formed near a bonding pad on a peripheral circuit region in a semiconductor device.
FIG. 1 shows a conventional ESD equivalence signal circuit 4 and a conventional ESD protection circuit 6 with a bonding pad 8 in a semiconductor device. Here, the ESD equivalence signal circuit 4, a typical RLC circuit, includes resistance "R", reactance "L" and a capacitor "C". The ESD protection circuit 6 includes first and second protection circuits 10 and 12 and a diffusion resistance Rd disposed between the first and second protection circuits 10 and 12.
The first and second protection circuits 10 and 12 should operate within an extremely short time in order to reduce any overload applied to an internal circuit of the semiconductor device. The first protection circuit 10, which is a protection means as shown in FIG. 2, includes a field oxide film 14. The second protection circuit 12 includes a transistor having a thin gate oxide film between a gate electrode 15 and a semiconductor substrate 13.
Referring to FIG. 2, in the first protection circuit, the overload applied to a pad is removed using a bipolar snapback conduction phenomenon generated between n.sup.+ doping regions 9 through the semiconductor substrate 13. However, if the overload is not completely removed from the first protection circuit, the overload is drawn to the supply voltage Vss by a bipolar conduction phenomenon generated between n.sup.+ doping regions 9a of the second protection circuit through the semiconductor substrate 13. Accordingly, in the ESD protection circuit, it is important to use an optimal diffusion resistance "Rd" between the first and the second protection circuits and to optimize the size and drain structure of the device forming the second protection circuit. To address the above-described necessity, a conventional technology developed by C. Duvvury et.al has been announced under the title of "ESD phenomena in graded junction device" from IEEE/IRPS 1989.
In most conventional methods, the ESD characteristic is proved through drain engineering or the reduction of the gate length to reduce the width of a base during bipolar operation.
FIG. 3 is a table showing how the characteristics of an ESD protection circuit vary according to the doping concentration of a source and drain region, i.e., an ESD voltage, substrate current, drain saturation current and snapback voltage. Referring to the table, doping of the source/drain region is divided into five grades of A to E, where the doping concentration increases from grade A to grade E. As the doping concentration increases, the snapback voltage, i.e. the voltage at which the snapback phenomenon begins, is reduced by 16.about.22% from a maximum of 12.8V to a minimum of 10.0V. Also, the ESD voltage V(ESD) is increased by 24.about.30% from the minimum of 3,600.+-.200V to the maximum of 5,175.+-.55V. However, undesirable leakage substrate current is increased by 25.about.35% from 1.36 .mu.A/.mu.M to the maximum 2.26 .mu.A/.mu.M. The saturation current of a MOS transistor, Idsat, is in an acceptable range.
FIG. 4 is a graph showing each snapback voltage in the cases of grade A and grade C, where the symbol ".box-solid." represents grade A and the symbol ".quadrature." represents grade C. Referring to FIG. 4, it can be seen that grade C, which has a doping concentration that is relatively higher than that of grade A, has a snapback voltage that is lower than that of grade A.
A conventional method for forming an ESD protection circuit region will be described in detail with reference to the accompanying drawings.
FIGS. 5 through 7 are sequential views showing a conventional method for manufacturing a semiconductor device. FIG. 5 shows a portion of a semiconductor memory circuit including a cell array region and peripheral circuit region. Region "A" forms an ESD protection circuit and a region "B" is a typical peripheral circuit region where NMOS transistors and PMOS transistors are to be formed. First, the semiconductor substrate 16 is divided into the typical peripheral circuit region "B", the ESD protection region "A", and the cell array region (not shown). Next, each region of the semiconductor substrate 16 is defined by an active region and a nonactive region, i.e., a field region, and then a field oxide film 18 is formed on the field region. The field oxide film can be formed as any one of a LOCOS type, a trench type, a SEPOX type and so on. The field oxide film 18 is formed, and then a thin buffer oxide film 20 is grown on the entire surface of the semiconductor silicon substrate 16.
FIG. 6 shows a step of forming a P-well on the ESD protection region "A" and typical peripheral circuit region "B". First, a first mask pattern 22 is formed on a semiconductor substrate 16. The first mask pattern 22 defines a region where an NMOS transistor is to be formed on the peripheral circuit region B. Next, impurities of P-type conductivity are ion-implanted into the entire surface of the resultant structure with energy enough to form an impurity layer under the field oxide film 18. As a result, a deep first impurity layer 24, i.e., a P-well, is formed in a portion of the semiconductor substrate 16 exposed by the first mask pattern 22. Then, impurities of P-type conductivity are ion-implanted into the semiconductor substrate 16 to form a second impurity layer 26, i.e., an N-field (P-type) channel stop region shallower than the depth of the P-well. At this stage, the second impurity layer 26 is formed with a doping concentration of about 1.times.10.sup.17 atoms/cm.sup.3.
Then, impurities of P-type conductivity are ion-implanted in order to control the threshold voltage of a MOS transistor, to thereby form a third impurity layer 28 which is shallower than the depths of the first and second impurity layers 24 and 26. The depth of the third impurity layer 28 is kept shallow by using a low implantation energy. Accordingly, the third impurity layer 28 exists only in the active region between the field oxide films 18.
An NMOS transistor is formed on a portion of the semiconductor substrate 16 not masked by the first mask pattern 22. The order for forming the first, second and third impurity layers 24, 26 and 28 can be changed.
FIG. 7 shows a step of forming an N-well where a PMOS transistor is to be formed. First, the first mask pattern 22 of FIG. 6 is removed. Then, a second mask pattern 30 is formed on the semiconductor substrate 16 for defining the ESD protection circuit region "A" and a region where the P-well is formed. Impurities of an N-type conductivity are ion-implanted with high energy into the region of senmiconductor substrate 16 exposed by the second mask pattern 30. A deep fourth impurity layer 32, i.e., an N-well, is formed in the semiconductor substrate 16 on the region exposed by second mask pattern 30. The impurities used for forming the fourth impurity layer 32 are implanted with high enough energy to pass through the field oxide film 18. Accordingly, the fourth impurity layer 32 exists under the field region of the portion which is not masked by the second mask pattern 30 as well as the active region thereof.
Impurities of N-type conductivity are subsequently ion-implanted, to thereby form a fifth impurity layer 34 of N-type conductivity, i.e., a P-field channel stop region, which is shallower than the depth of the fourth impurity layer 32. The fifth impurity layer 34 is formed deeply under the active region of the semiconductor substrate 16, while formed shallowly under the field oxide film 18 of the field region. Next, a sixth impurity layer 36 is formed shallower than the depth of the fifth impurity layer 34, only on an active region of the semiconductor substrate 16. The sixth impurity layer 36 controls the threshold voltage of the transistor. Next, the second mask pattern 30 is eliminated, and then transistors are formed on each region of the semiconductor substrate 16 in the usual manner.
As described above, in an ESD protection circuit region formed by a conventional method, the length of the gate can be reduced when the transistor is formed, thereby increasing the ESD voltage. However, when the first to third impurity layers 24, 26 and 28 of FIG. 7 are formed, the resistance of the substrate decreases due to the increase in impurity concentration in the substrate, and thus, the leakage current increases.